In a traditional liquid crystal display device, an electric field is used to control the orientation of liquid crystal molecules to display an image. As shown in FIG. 1, the traditional liquid crystal display device 100 includes a liquid crystal panel 101, a plurality of data lines 102 formed on the liquid crystal panel 101, a plurality of gate lines 103, a plurality of common lines 104, a plurality of gate line trigger circuits (including a trigger circuit Gate 1, a trigger circuit Gate 2, a trigger circuit Gate 3, a trigger circuit Gate 4 . . . a trigger circuit Gate n−1, and a trigger circuit Gate n), and a plurality of common line trigger circuits (including a trigger circuit COM 1, a trigger circuit COM 2, a trigger circuit COM 3, a trigger circuit COM 4 . . . a trigger circuit COM n−1, and a trigger circuit COM n).
In FIG. 1, a first direction is defined by the vertical direction, while a second direction is defined by the horizontal direction. The data lines 102 extend in the first direction, the gate lines 103 extend in the second direction and intersect with the data lines 102, and the common lines 104 are in parallel with the gate lines 103 and intersect with the data lines 102. The regions defined by the plurality of data lines 102 and the plurality of gate lines 103 are used as display regions. The liquid crystal panel 101 is provided with Thin-Film-Transistors (TFTs), each of which is used to drive a liquid crystal element CLC located at the intersection. Furthermore, the liquid crystal panel 101 is equipped with storage capacitors CST for maintaining the voltages of the liquid crystal elements CLC. The TFT is turned on if its gate is applied with a gate voltage by the gate line 103. At this time, if a drive voltage is provided to a pixel electrode 107 via the data line 102 and a common voltage is provided to a common electrode 108 via the common line 104, an electric field is generated on the liquid crystal element CLC to change the arrangement of the liquid crystal molecules, so as to control the light transmittance of the liquid crystal element CLC.
In the liquid crystal panel 101, one end of each of the gate lines 103 is connected to one gate line trigger circuit which is used to selectively provide a gate voltage to the gate line 103; and the other end of the gate line 103 is connected to a common line trigger circuit in the row of the gate line, and is used to trigger the common line trigger circuit and to selectively provide a common voltage to the common line 104 in the row. The gate line trigger circuit is located on one side of the display region and the common line trigger circuit is located on the other side of the display region. When a common voltage is applied to the common electrode and a gate voltage is inputted to apply a data voltage to the pixel electrode 107, the charging of the storage capacitor CST is started, and the charging ends once the gate voltage is removed and the TFT is turned off. Here, the time for the charging of the storage capacitor CST is referred to as charging time. After the sufficient charging time, the voltage across the storage capacitors CST is equal to the difference between the data voltage and the common voltage. After the TFT is turned off, the storage capacitor CST maintains the orientation of the liquid crystal molecules with its voltage.
There exists latency for the gate voltage to be transferred from the leftmost pixel to the rightmost pixel. The gate voltage transferred to the rightmost pixel triggers the common line trigger circuit, and then the triggered common line trigger circuit provides the common voltage to the common line. Likewise, there exists latency for the common voltage to be transferred from the rightmost pixel to the leftmost pixel. All the above latency results in that, after a gate voltage is applied to the TFT, the common voltage is applied to the common electrode 108 after certain delay time. The above latency is an RC delay which is significantly impacted by resistance of the gate line and the common line as well as the related parasitic capacitance. Particularly, if the resistance is increased, the related parasitic capacitance is increased, and the latency is lengthened. The presence of the above latency shortens the charging time of the storage capacitors CST, as a result, the storage capacitors CST cannot be charged to a predetermined voltage value and hence the liquid crystal molecules cannot be rotated to predetermined positions to implement the intended display.
To maintain the polarities of the liquid crystal molecules, the liquid crystal display device may be driven by a driving approach with an unchanged common voltage and a driving approach with inverted common voltages. FIG. 2 shows a time sequence for the driving approach with inverted common voltages. As shown in FIG. 2, after each gate line is applied by a gate voltage, the applying of a common voltage to the common voltage line is later than the applying of the gate voltage because of the presence of the latency t, therefore the charging time T of the storage capacitors CST is shortened, such that the voltage of the storage capacitor CST cannot reach the difference between the data voltage and the common voltage, and hence the display effect is degraded.
With the increasing improved resolution of the liquid crystal display device, more and more gate lines and common lines are distributed on the liquid crystal panel, and the charging time for each storage capacitor CST under the same refresh frequency is increasingly shortened. Meanwhile, a high aperture ratio of the liquid crystal panel requires for thinner gate lines and common lines, which causes larger resistance and hence lengthened RC delay. Based on the above two reasons, the effective charging time for the storage capacitor CST is increasingly shortened, which has become a substantial problem degrading the resolution of the liquid crystal display device.
Therefore, it is necessary to develop a liquid crystal display device and a driving method of the liquid crystal display device, for reducing or eliminating the impact of the above latency to the storage capacitor CST.